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microphone
...
master
5 changed files with 0 additions and 234 deletions
1
Cargo.lock
generated
1
Cargo.lock
generated
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@ -115,7 +115,6 @@ dependencies = [
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"bitmask-enum",
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"bitmask-enum",
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"embedded-hal-bus",
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"embedded-hal-bus",
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"esp-hal",
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"esp-hal",
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"esp32s3",
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"mipidsi",
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"mipidsi",
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"thiserror",
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"thiserror",
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]
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]
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@ -21,7 +21,6 @@ bitflags = "2.9.1"
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bitmask-enum = "2.2.5"
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bitmask-enum = "2.2.5"
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embedded-hal-bus = "0.3.0"
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embedded-hal-bus = "0.3.0"
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esp-hal = {version = "=1.0.0-beta.1", features = ["esp32s3", "unstable"]}
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esp-hal = {version = "=1.0.0-beta.1", features = ["esp32s3", "unstable"]}
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esp32s3 = "0.32.0"
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mipidsi = "0.9.0"
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mipidsi = "0.9.0"
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thiserror = {version = "2.0.11", default-features = false}
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thiserror = {version = "2.0.11", default-features = false}
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@ -2,7 +2,6 @@
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pub mod display;
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pub mod display;
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pub mod keyboard;
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pub mod keyboard;
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pub mod microphone;
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#[cfg(test)]
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#[cfg(test)]
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fn main() {}
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fn main() {}
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@ -1,38 +0,0 @@
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use crate::microphone::clock_calculation::{calculate_clock, set_clock};
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mod clock_calculation;
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fn mic(i2s0: esp_hal::peripherals::I2S0) {
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drop(i2s0);
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let i2s0 = unsafe { esp32s3::I2S0::steal() };
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// clear clock config register
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// i2s0.rx_clkm_conf().reset();
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// i2s0.rx_conf().reset();
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set_clock(
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&i2s0,
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calculate_clock(esp_hal::time::Rate::from_mhz(2), 1, 16),
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);
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let gpio = unsafe { esp32s3::GPIO::steal() };
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gpio.func46_in_sel_cfg().modify(|_, w| w.)
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// let io_mux = unsafe { esp32s3::IO_MUX::steal() };
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// io_mux.gpio(46).modify(|_, w| w.)
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i2s0.rx_conf()
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.modify(|_, w| w.rx_reset().set_bit().rx_fifo_reset().set_bit());
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i2s0.rx_conf()
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.modify(|_, w| w.rx_reset().clear_bit().rx_fifo_reset().clear_bit());
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i2s0.rx_conf().modify(|_, w| w.rx_ws_idle_pol().clear_bit());
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i2s0.rx_conf1()
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.modify(|_, w| unsafe { w.rx_half_sample_bits().bits(15).rx_bits_mod().bits(15) });
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// Enable PDM mode
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i2s0.rx_conf().modify(|_, w| w.rx_pdm_en().set_bit());
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}
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@ -1,193 +0,0 @@
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//! This module contains code lifted from esp-rs/esp-hal,
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//! which has been slightly modified for use in this library.
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//!
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//! ## License
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//!
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//! Copyright 2021 esp-rs
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//!
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//! Permission is hereby granted, free of charge, to any
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//! person obtaining a copy of this software and associated
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//! documentation files (the "Software"), to deal in the
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//! Software without restriction, including without
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//! limitation the rights to use, copy, modify, merge,
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//! publish, distribute, sublicense, and/or sell copies of
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//! the Software, and to permit persons to whom the Software
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//! is furnished to do so, subject to the following
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//! conditions:
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//!
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//! The above copyright notice and this permission notice
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//! shall be included in all copies or substantial portions
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//! of the Software.
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//!
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//! THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF
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//! ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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//! TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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//! PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
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//! SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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//! CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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//! OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
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//! IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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//! DEALINGS IN THE SOFTWARE.
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use esp_hal::time::Rate;
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pub(super) struct I2sClockDividers {
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mclk_divider: u32,
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bclk_divider: u32,
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denominator: u32,
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numerator: u32,
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}
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/// The default clock source for I2S operations.
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const I2S_DEFAULT_CLK_SRC: u8 = 2;
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const I2S_SCLK: u32 = 160_000_000;
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const I2S_LL_MCLK_DIVIDER_BIT_WIDTH: usize = 6;
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const I2S_LL_MCLK_DIVIDER_MAX: usize = (1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1;
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pub(super) fn calculate_clock(sample_rate: Rate, channels: u8, data_bits: u8) -> I2sClockDividers {
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// this loosely corresponds to `i2s_std_calculate_clock` and
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// `i2s_ll_tx_set_mclk` in esp-idf
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//
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// main difference is we are using fixed-point arithmetic here
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// If data_bits is a power of two, use 256 as the mclk_multiple
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// If data_bits is 24, use 192 (24 * 8) as the mclk_multiple
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let mclk_multiple = if data_bits == 24 { 192 } else { 256 };
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let sclk = I2S_SCLK; // for now it's fixed 160MHz
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let rate = sample_rate.as_hz();
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let bclk = rate * channels as u32 * data_bits as u32;
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let mclk = rate * mclk_multiple;
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let bclk_divider = mclk / bclk;
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let mut mclk_divider = sclk / mclk;
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let mut ma: u32;
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let mut mb: u32;
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let mut denominator: u32 = 0;
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let mut numerator: u32 = 0;
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let freq_diff = sclk.abs_diff(mclk * mclk_divider);
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if freq_diff != 0 {
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let decimal = freq_diff as u64 * 10000 / mclk as u64;
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// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 /
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// 126.0
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if decimal > 1250000 / 126 {
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mclk_divider += 1;
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} else {
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let mut min: u32 = !0;
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for a in 2..=I2S_LL_MCLK_DIVIDER_MAX {
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let b = (a as u64) * (freq_diff as u64 * 10000u64 / mclk as u64) + 5000;
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ma = ((freq_diff as u64 * 10000u64 * a as u64) / 10000) as u32;
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mb = (mclk as u64 * (b / 10000)) as u32;
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if ma == mb {
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denominator = a as u32;
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numerator = (b / 10000) as u32;
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break;
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}
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if mb.abs_diff(ma) < min {
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denominator = a as u32;
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numerator = b as u32;
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min = mb.abs_diff(ma);
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}
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}
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}
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}
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I2sClockDividers {
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mclk_divider,
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bclk_divider,
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denominator,
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numerator,
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}
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}
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pub(super) fn set_clock(i2s0: &esp32s3::I2S0, clock_settings: I2sClockDividers) {
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let clkm_div_x: u32;
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let clkm_div_y: u32;
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let clkm_div_z: u32;
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let clkm_div_yn1: u32;
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if clock_settings.denominator == 0 || clock_settings.numerator == 0 {
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clkm_div_x = 0;
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clkm_div_y = 0;
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clkm_div_z = 0;
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clkm_div_yn1 = 1;
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} else if clock_settings.numerator > clock_settings.denominator / 2 {
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clkm_div_x = clock_settings
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.denominator
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.overflowing_div(
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clock_settings
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.denominator
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.overflowing_sub(clock_settings.numerator)
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.0,
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)
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.0
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.overflowing_sub(1)
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.0;
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clkm_div_y = clock_settings.denominator
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% (clock_settings
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.denominator
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.overflowing_sub(clock_settings.numerator)
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.0);
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clkm_div_z = clock_settings
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.denominator
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.overflowing_sub(clock_settings.numerator)
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.0;
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clkm_div_yn1 = 1;
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} else {
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clkm_div_x = clock_settings.denominator / clock_settings.numerator - 1;
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clkm_div_y = clock_settings.denominator % clock_settings.numerator;
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clkm_div_z = clock_settings.numerator;
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clkm_div_yn1 = 0;
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}
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i2s0.tx_clkm_div_conf().modify(|_, w| unsafe {
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w.tx_clkm_div_x().bits(clkm_div_x as u16);
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w.tx_clkm_div_y().bits(clkm_div_y as u16);
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w.tx_clkm_div_yn1().bit(clkm_div_yn1 != 0);
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w.tx_clkm_div_z().bits(clkm_div_z as u16)
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});
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i2s0.tx_clkm_conf().modify(|_, w| unsafe {
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w.clk_en().set_bit();
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w.tx_clk_active().set_bit();
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w.tx_clk_sel()
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.bits(I2S_DEFAULT_CLK_SRC) // for now fixed at 160MHz
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;
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w.tx_clkm_div_num().bits(clock_settings.mclk_divider as u8)
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});
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i2s0.tx_conf1().modify(|_, w| unsafe {
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w.tx_bck_div_num()
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.bits((clock_settings.bclk_divider - 1) as u8)
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});
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i2s0.rx_clkm_div_conf().modify(|_, w| unsafe {
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w.rx_clkm_div_x().bits(clkm_div_x as u16);
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w.rx_clkm_div_y().bits(clkm_div_y as u16);
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w.rx_clkm_div_yn1().bit(clkm_div_yn1 != 0);
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w.rx_clkm_div_z().bits(clkm_div_z as u16)
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});
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i2s0.rx_clkm_conf().modify(|_, w| unsafe {
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w.rx_clk_active().set_bit();
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// for now fixed at 160MHz
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w.rx_clk_sel()
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.bits(I2S_DEFAULT_CLK_SRC);
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w.rx_clkm_div_num().bits(clock_settings.mclk_divider as u8);
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w.mclk_sel().bit(true)
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});
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i2s0.rx_conf1().modify(|_, w| unsafe {
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w.rx_bck_div_num()
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.bits((clock_settings.bclk_divider - 1) as u8)
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});
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}
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